Industry Background

Novellus Systems, Inc.

Semiconductor Equipment Industry Backgrounder

Novellus Systems, Inc. develops, manufactures, sells and supports equipment used in the fabrication of integrated circuits. The customers for these products are semiconductor manufacturers who are either building chips for their own production, or who are offering IC manufacturing services to other third party businesses. Over the past twenty years, the semiconductor industry has grown rapidly as a result of increasing demand for personal computers, the expansion of the Internet and the telecommunications industry, and the emergence of new applications in consumer electronics.

Integrated circuits are generally built on a silicon wafer base and include a large number of different components, such as transistors, capacitors and other electronic devices that are connected by multiple layers of wiring, or interconnects. To build an integrated circuit, transistors are first created on the surface of the silicon wafer. The wiring and insulating structures are then added as multiple thin-film layers through a series of manufacturing process steps. Typically, a first layer of dielectric (insulating) material is deposited on top of the formed transistors. Subsequent layers of metal (historically, aluminum) are formed on top of this base layer, etched to create the conductive lines that carry the electricity, and then filled with dielectric material to create the necessary insulators between the lines, in a manufacturing process called subtractive aluminum. When copper wires are being constructed, the manufacturing process, called copper damascene, is a mirror image of that described above: the insulator (dielectric) is etched, and the copper wiring is created in the etched insulator via a high-technology electroplating process called electrochemical deposition. Building either copper or aluminum wiring requires these manufacturing steps to be repeated many times: advanced chip designs may require as many as 500 process steps.

Several technological trends characterize semiconductor manufacturing. Perhaps the most prominent of these trends is the increasing density of the integrated circuit. Moore's Law, first postulated in the mid-1960s and still substantially accurate 40 years later, states that the density of circuitry on an individual semiconductor chip doubles every 18 months. Today's advanced devices are being manufactured with line widths as small as 65 nanometers, and with up to ten layers of interconnect circuitry. By increasing circuit density, manufacturers can pack more electronic components on a chip and thereby provide higher performance and value.

Another trend worth noting is the transition to copper wiring from aluminum wiring as the primary conductive material in semiconductor devices. Copper has a lower electrical resistance value than aluminum, which provides a number of performance advantages. Because of the superior properties of copper, a chip made with copper may need only half as many metal layers as one made with aluminum, providing considerable reduction in manufacturing cost. In addition, copper wiring produces a substantial improvement in device performance and a significant reduction in power requirements in comparison to aluminum.

A similar transition is underway from traditional silicon oxide films to dielectric insulators with a low dielectric constant, or low-k. Low-k dielectrics are better at limiting the capacitance between metal lines in a device, which improves the speed and performance of the chip. However, low-k materials are also more fragile than silicon oxide, and this poses a host of new challenges to the semiconductor industry in integrating the new materials into a manufacturing process flow.

Another important trend is the move to larger wafer sizes. Chipmakers are now migrating to larger, 300 mm wafers because of the potential manufacturing cost advantages of these larger wafers compared to 200 mm. The 300 mm wafers provide up to 2.25 times the number of chips per wafer, and hence may provide significant economies of scale in the manufacturing process.

These trends shape the equipment and process demands of our customers. Our customers generally measure the cost and performance of their production equipment in terms of "cost per wafer," a ratio determined by factoring in the costs for acquisition and installation of a system, operating costs, and net throughput rate. A system with higher net throughput allows a manufacturer to recover the purchase price over a greater number of wafers, thereby reducing the cost of ownership of the system on a per-wafer basis. Yield and film qualities are also significant factors in selecting processing equipment. The increased cost of larger and more complex semiconductor wafers have made high yields extremely important to our customers. To achieve elevated yields and better film quality, systems must be able to repeat a process consistently and reliably. This characteristic, known as repeatability, is critical in achieving commercially acceptable yields. Systems that operate at desired throughput rates without approaching critical tolerance limits can achieve repeatability more easily.

These changes in manufacturing geometries and materials have significantly increased the cost and performance requirements of the equipment used to manufacture semiconductor devices. An advanced 300 millimeter wafer fabrication line, for example, can cost more than $2 billion, representing a substantial increase over the costs associated with previous-generation facilities. At the same time, demand for advanced technology continues to grow as the industry adapts to working with ever shrinking nodes and faster technology cycles. As a result, chipmakers are focused on balancing their need for innovative technology while optimizing each unit process involved in the manufacturing cycle. This transition-and the opportunities that accompany it-are at the heart of Novellus' strategy to build on its productivity advantage while offering cutting edge technology to the world's leading semiconductor device manufacturers-thus providing a clear VALUE differentiator for Novellus in a rapidly-changing industry.

Technical Glossary of Terms

Barrier is a thin layer of conducting film which prevents the primary conductor, either aluminum or copper, from migrating into the oxide or silicon. A secondary purpose of the barrier is to promote adhesion of the primary conductor.

Chemical Mechanical Polishing or Planarization (CMP) is a process that uses a slurry and circular pad to make the surface of the wafer flat. In a very gross sense, to CMP a wafer is like sanding a dining room table to a fine finish with an orbital sander.

Chemical Vapor Deposition (CVD) processes are used to deposit dielectric films in an integrated circuit, as well as for depositing conductive metal layers, particularly those with line widths too small for effective deposition with PVD or other deposition technologies. CVD may be thought of as a high-tech spray painting process where paint vapor coats all the surfaces uniformly.

Clean is the removal of all undesirable materials from the surface of the wafer without causing damage to the exposed layers. This includes the removal of photoresist and post-etch polymers. Cleans are performed with both wet and dry cleaning technologies.

Copper Damascene/Dual Damascene is a process where vias and trenches are etched into insulating material. Copper is then filled into all the vias and trenches and sanded back so the conducting materials are only left in the vias and trenches.

Deposition is the process in which a film of either electrically insulating or electrically conductive material is deposited on the surface of a wafer.

Dielectrics are materials that are non-conductive and used as insulators in integrated circuits. Commonly used materials include silicon oxide and silicon nitride.

Dry clean is usually a plasma process used to remove photoresist and residues from the wafer surface.

Electrofill,  Novellus' high technology electrochemical deposition process, deposits high quality copper films into the deep, narrow trenches that form the interconnects or copper wiring in advanced ICs.

Etch is a chemical reactive process for selectively removing material on a silicon wafer during semiconductor manufacturing.

Front Opening Unified Pod (FOUP) is a plastic box used in the semiconductor factory to transport wafers from processing machine to processing machine. It has standard dimensions and openings that have been agreed upon by all semiconductor manufacturers.

Hollow Cathode Magnetron (HCM) is a patented source technology for sputtering material onto the surface of the wafer. The HCM develops a plasma, like you see in a fluorescent light. The excited plasma vaporizes material of a target held in the HCM, which is directed at the wafer where it condenses and sticks.

High Density Plasma (HDP) is a gas that has been excited to a level that electrons are leaving the outer orbits of each atom of the gas. When the electron leaves the orbit, it emits light. This is the process that illuminates fluorescent light bulbs. Novellus HDP (deposited on the SPEED platform) however, is much denser-there are more ions and electrons in a smaller volume excited with much higher voltages.

Interconnects are metal film layers that "wire" together the millions of transistors included in an integrated circuit.

Low-k   k is the dielectric constant of the insulating film being deposited on a substrate.  The film is "low-k" if its dielectric constant is less than that of silicon dioxide (SiO2), which has a k-value of about 4.0.  An "ultra low-k" film has a significantly lower dielectric constant, typically below 2.0.  By comparison, air, as an insulator, has a k-value of 1.0.

Micron is a unit of length, about 40-millionths of an inch. A human hair is approximately 100 microns wide.

Organosilicate Glass (OSG) is a carbon-doped low-k material with a k-value of ~ 2.7

Passivation is the final layer in a semiconductor device that forms a hermetic seal over the circuitry. Plasma nitride and silicon dioxide are the primary materials used in this process.

Photolithography is the process by which a circuit pattern is transferred to a wafer.

Photoresist is a light-sensitive organic polymer that is used in the photolithography process to develop a pattern which masks some areas of the film to protect them during the etch process.

Photoresist removal is the removal of all remaining photoresist left on the wafer after the implant or etch process.

Physical Vapor Deposition (PVD), also known as sputtering, is used in a subtractive aluminum manufacturing process to deposit the thin conductive films that wire the transistors together. PVD is also used in a copper damascene manufacturing process to deposit the copper barrier layer (which helps to contain the copper lines in the device) and the copper seed layer (which serves as a nucleation layer on which the copper conductive fill "grows").

Plasmas are ionized gases representing the fourth state of matter. In the deposition process plasmas are often generated using a radio frequency (RF) energy field. When used for photoresist and residue removal the plasmas may be RF or microwave frequencies.

Pulsed Deposition Layer (PDL) technology is Novellus' productive answer to an ALD (atomic layer deposition) process. With ALD each gas must be completely purged from a reaction chamber before a new gas is introduced, a process that is inherently slow. (In contrast, the CVD approach uses more than one gas in the reactor at a time). With the PDL approach the chamber purging starts with the introduction of the second gas, resulting in an ALD-like film quality with the high throughput and low cost of the CVD approach.

Pulsed Nucleation Layer (PNL) technology is a variant of Novellus' PDL approach that is used specifically for depositing tungsten films on the ALTUS system.

Residue is the post-etch polymers on the wafer left after a post-etch process such as STI-etch, gate-etch, metal-etch, via-etch, trench-etch, and contact-etch.

Residue removal is the removal of all remaining residues left on the wafer after the implant or etch process.

Seed Layer is a conductive film laid down prior to copper Electrofill to serve as an adhesion layer during the Electrofill process.

Semiconductor is a material with an electrical conductivity midway between a metal (conductor) and an insulator (non-conductor).

Silicon Dioxide (SiO2) is a silicon/oxygen film most frequently used for dielectric applications.

Silicon Nitride is a silicon/nitrogen film frequently used as a final passivation layer.

Strip is also known as photoresist removal or ashing.

Wet clean employs a variety of equipment such as wet benches, spin/rinse/dryers, brush scrubbers, etc. to clean the wafer surface after several manufacturing steps, including photoresist removal, etch, and CMP.