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NOVELLUS' ASHABLE HARDMASK (AHM™) PECVD FILMS ENABLE SUB-32NM LITHOGRAPHIC PATTERNING
Nov 24, 2009 |
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San Jose, California - November 24, 2009 - Novellus Systems (NASDAQ: NVLS) has developed a suite of ashable hardmask (AHM) films that have up to 25 percent greater etch selectivity compared to similar amorphous carbon films in use by the industry today. This highly selective and transparent (HST) AHM family of films has demonstrated die yield im...
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NOVELLUS IMPROVES TUNGSTEN RESISTIVITY PERFORMANCE WITH ADVANCED LRWXT™ PROCESS
Nov 3, 2009 |
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San Jose, California - November 3, 2009 - Novellus Systems (NASDAQ: NVLS) announced today that it has developed a new tungsten deposition process, called LRWxT, that can effectively reduce contact and line resistance at the 3Xnm technology node compared to conventional tungsten chemical vapor deposition (CVD-W) technology. The new approach uses ...
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NOVELLUS SYSTEMS LAUNCHES SABRE® EXCEL™ FOR 22NM COPPER ELECTROPLATING
Oct 20, 2009 |
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San Jose, California – October 20, 2009 – Novellus Systems (NASDAQ: NVLS) today introduced the SABRE Excel, an advanced copper electroplating system designed to provide industry-leading fill and defect density performance for the 22nm technology node and beyond. SABRE Excel builds upon the production-proven SABRE, a platform already em...
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NOVELLUS' SPEED® MAX HDP-CVD DIELECTRIC GAPFILL SYSTEM EXTENDS STI APPLICATION TO 32NM
Oct 5, 2009 |
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San Jose, Calif. - October 5, 2009 -- Novellus Systems (NASDAQ: NVLS) today announced that it has developed a manufacturing process to extend the company's SPEED Max shallow trench isolation (STI) application to the 32nm technology node. The new process technology takes advantage of the dynamic profile control (DPC™) of the SPEED Max high ...
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NOVELLUS SYSTEMS RECEIVES "BEST IN VALUE" SUPPLIER AWARD FROM SAMSUNG ELECTRONICS
Oct 1, 2009 |
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San Jose, California, - October 1, 2009 - Novellus Systems (NASDAQ: NVLS) announced today that it has received a "Best in Value" supplier award from Samsung Electronics at their Supplier Appreciation Day, held in Santa Clara, California on September 16, 2009. The "Best in Value" designation is the highest honor bestowed by Samsung on a supplier....
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NOVELLUS' SOLA® ULTRA-VIOLET THERMAL PROCESSING SYSTEM PROVIDES OPTIMUM ULK FILM INTEGRATION AT 32NM
Sep 22, 2009 |
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San Jose, Calif. - September 22, 2009 - Novellus Systems (NASDAQ: NVLS) announced today that it has developed a multiple wavelength UV Thermal Processing (UVTP) treatment on the company's SOLA® platform that results in a 25 percent improvement in film hardness compared to a single wavelength treatment of the same k-value dielectri...
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NOVELLUS SYSTEMS AND UALBANY NANOCOLLEGE LAUNCH $20 MILLION NANOELECTRONICS R&D PARTNERSHIP
Jul 13, 2009 |
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Albany, NY--July 13, 2009 - The College of Nanoscale Science and Engineering (CNSE) at the University at Albany, and Novellus Systems, Inc. (NASDAQ: NVLS), a Silicon Valley-based provider of advanced process equipment for the global nanoelectronics industry, announced today that they have formed a $20 million partnership to conduct next-generati...
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NOVELLUS' ADVANCED COPPER SEED TECHNOLOGY EXTENDS PVD INTERCONNECT TO SUB-2XNM NODE
Jul 13, 2009 |
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San Jose, Calif. - July 13, 2009 - Novellus Systems (NASDAQ:NVLS) announced today that it has developed an advanced Hollow Cathode Magnetron (HCM®) IONX™ PVD copper seed process that will enable copper interconnects...
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NOVELLUS' PETER WOLTERS DIVISION DEVELOPS 22NM DOUBLE-SIDED SILICON WAFER POLISH PROCESS
Jun 23, 2009 |
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San Jose, Calif. - June 23, 2009- To address the challenges of wafer polishing at future technology nodes, Peter Wolters GmbH, a wholly-owned subsidiary of Novellus Systems (NASDAQ:NVLS), has recently developed advanced polishing technology for its MicroLine AC 1500-P³ and AC 2000-P³ double-sided silicon wafer polishing (DSP) systems t...
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NOVELLUS' ULTRA LOW DIELECTRIC CONSTANT MATERIALS ENABLE 32NM DEVICE INTEGRATION
Jun 18, 2009 |
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NOVELLUS' SUB-45NM HDP GAPFILL PROCESS PROVIDES 3X REDUCTION IN MEDIAN DEFECT DENSITY
Jun 4, 2009 |
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San Jose, Calif. - June 4, 2009 - Novellus Systems (NASDAQ: NVLS) has developed a sub-45nm, in-situ chamber clean process on the SPEED Max High Density Plasma (HDP) CVD gapfill platform that significantly reduces defect density and out-of-control (OOC) particle events. The key components of this process include efficient NF3 delivery and optimiz...
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NOVELLUS' HCM® IONX™ XL TA(N) BARRIER TECHNOLOGY ENABLES 3X/2XNM MEMORY TRANSITION TO COPPER
May 27, 2009 |
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San Jose, Calif. - May 27, 2009 - Ten years after the introduction of copper metallization for logic device manufacturing, Physical Vapor Deposition (PVD) copper barrier-seed and copper electrochemical deposition (ECD) ...
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NOVELLUS DEVELOPS RESIDUE-FREE, 3X/2XNM HIGH DOSE IMPLANT STRIP PROCESS
May 13, 2009 |
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San Jose, Calif. - May 13, 2009 - As device performance requirements increase at the 3xnm technology node and beyond, the requirements for photoresist strip and clean are changing significantly. Shallower junctions and more abrupt gate electrode profiles are driving lower energy, higher dose implant steps, with doses typically in the 1E15cm...
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NOVELLUS' 32NM UV-ABSORBING DIELECTRIC FILMS KEY TO IMPROVED DEVICE RELIABILITY
May 6, 2009 |
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San Jose, Calif. - May 6, 2009 - In order for RC delay to continue to scale in accordance with the International Technology Roadmap for Semiconductors (ITRS), device manufacturers are integrating ultra-low k (ULK) dielectric materials into their 32 nm process flows. At the same time, UltraViolet Thermal Processing (UVTP) is being introduced into...
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NOVELLUS' COOLFILL CVD PROCESS ADVANCES TUNGSTEN FILL FOR SUB-32NM HIGH ASPECT RATIO STRUCTURES
Apr 16, 2009 |
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San Jose, Calif. - April 16, 2009- As semiconductor devices scale to the 32nm technology node and beyond, shrinking contact and via dimensions make chemical vapor deposition (CVD) of tungsten more challenging. Increasing aspect ratios can lead to voids or large seams within device features, resulting in lower yields and decreased performance in ...
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NOVELLUS' SUPPRESSION-ENHANCED FILL™ TECHNOLOGY PROVIDES DEFECT-FREE 32NM COPPER INTERCONNECTS
Apr 9, 2009 |
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San Jose, Calif. – April 9, 2009 – Since the advent of copper damascene processing, achieving void-free fill of high aspect ratio interconnect features has been a key challenge for device manufacturers. Shrinking dimensions at each successive technology node have increased the complexity of the copper seed and electroplating processes, an...
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NOVELLUS' ULTRA-THIN DIELECTRIC DIFFUSION BARRIERS BOOST 32NM INTERCONNECT PERFORMANCE
Apr 1, 2009 |
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San Jose, Calif. - April 1, 2009 - In order to support the RC delay scaling required by the International Technology Roadmap for Semiconductors (ITRS), process designers have focused their attention on reducing the permittivity of dielectrics used in the interconnect stack. Research has shown that significant reduction in the permittivity of the...
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NOVELLUS' INNOVATIVE 32 NM DIELECTRIC TECHNOLOGIES ENABLE INTERCONNECT RC DELAY SCALING
Mar 18, 2009 |
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San Jose, Calif. - March 18, 2009 - In order for device performance to keep pace with Moore's Law, integrated circuit designers have had to drive node-to-node reductions in interconnect-related RC delay. Achieving this performance scaling has become increasingly challenging as interconnect spacing has decreased below 45nm. Over the past several ...
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NOVELLUS, ATMI AND ENTHONE INTRODUCE ENHANCED ELECTROCHEMICAL DEPOSITION PROCESS FOR COPPER
Mar 17, 2009 |
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