Semiconductor Manufacturing Overview
Integrated circuits are generally built on a silicon wafer base and include a large number of different components, such as transistors, capacitors and other electronic devices that are connected by multiple layers of wiring, or interconnects. To build an integrated circuit, transistors are first created on the surface of the silicon wafer. The wiring and insulating structures are then added as multiple thin-film layers through a series of manufacturing process steps. Typically, a first layer of dielectric (insulating) material is deposited on top of the formed transistors. Subsequent layers of metal (historically, aluminum) are formed on top of this base layer, etched to create the conductive lines that carry the electricity, and then filled with dielectric material to create the necessary insulators between the lines, in a manufacturing process called subtractive aluminum. Most advanced chips are now being constructed with copper interconnects, since copper has lower resistivity than aluminum at advanced technology nodes. When copper wires are being constructed, the manufacturing process, called copper damascene, is a mirror image of that described above: the insulator (dielectric) is etched, and the copper wiring is created in the etched insulator via a high-technology electroplating process called electrochemical deposition.
Regardless of whether an integrated circuit is made with copper or aluminum wiring, the manufacturing process steps must be repeated many times: advanced chip designs may require as many as 500 process steps. And, different Novellus products are used to manufacture different types of devices. Figure 1, below, shows the Novellus equipment used to manufacture a logic device, or microprocessor. Figure 2 shows the equipment used to build a DRAM-type memory device, and Figure 3 shows the equipment used to manufacture a NAND Flash memory device.
Manufacturing Process Technologies used at Novellus
Novellus has historically focused on a single segment of the chipmaking process: the deposition of the thin films used to create conductive metal lines and their surrounding insulators. As the company has grown, we’ve expanded into market segments that are adjacent to thin film deposition, including wafer surface preparation and wafer polishing (called chemical mechanical planarization). These process technologies are described below.
CVD (Chemical Vapor Deposition)
In the CVD process, chipmakers place silicon wafers in a reaction chamber, introduce a variety of pure and precisely metered gases into the chamber, and then add some form of energy to activate a chemical reaction that deposits a film on the wafer. The CVD process is the traditional method used to deposit dielectric films on wafers. Manufacturers also use CVD to deposit conductive metal layers, particularly tungsten, as it is difficult to deposit such layers on devices with very small features when using conventional PVD or other deposition technologies.
For depositing dielectric films, Novellus sells CVD products that use plasma as the energy source. The company offers two product lines, one based on plasma-enhanced chemical vapor deposition technology (PECVD), and the other based on high-density plasma chemical vapor deposition technology (HDP CVD). Novellus also offers a product line that addresses the market need for the CVD deposition of conductive tungsten metals.
PVD (Physical Vapor Deposition)
PVD, also known as “sputtering,” is a process where ions of an inert gas such as argon are electrically accelerated in a high vacuum toward a target of pure metal, such as tantalum or copper. Upon impact, the argon ions sputter off the target material, which is then deposited as a thin film on the silicon wafer. PVD processes are used to create the dielectric barrier and copper seed layers in a copper damascene manufacturing sequence, as well as the conductive aluminum interconnect in a subtractive aluminum manufacturing sequence. Novellus’ PVD product line is well-suited to both of these manufacturing sequences.
ECD (Electrochemical Deposition)
A manufacturing process called electrochemical deposition is used to build the copper primary conduction wires in advanced integrated circuits. In electrochemical deposition, a silicon wafer is immersed in a copper electrolytic solution in order to fill a structure that has been etched into the wafer’s insulating layer. The resulting copper conductive line “grows” upon the copper seed layer previously created by the PVD deposition step.
Surface Preparation
Surface Preparation includes the removal of photoresist residues that remain on the wafer after photolithographic patterning (called photoresist stripping), and subsequent cleaning of the wafer’s surface prior to the following deposition steps. Photoresist strip and clean processes represent an area of semiconductor manufacturing that is becoming increasingly important with the industry’s migration to copper conductive wiring. Both wet chemistry and dry chemistry (i.e., plasma based) cleaning technologies are used in the surface preparation process step. Novellus entered this application arena by acquiring GaSonics International in 2001, and today we’re one of the industry’s leading suppliers of dry chemistry surface preparation systems.
CMP (Chemical Mechanical Planarization)
Chemical Mechanical Planarization is essentially a high technology approach to sanding. CMP systems are used to polish the surface of a wafer after a deposition step to create a flat topography before moving on to subsequent manufacturing steps. Unlike the deposition process steps, the CMP process uses wet chemistries, in the form of polishing slurries, to remove unwanted materials from the wafer. Since copper is more difficult to polish and smooth than previous-generation aluminum interconnects, and the most advanced insulators (called low-k dielectrics) are much more porous than their predecessors, CMP has been elevated to the forefront of the enabling technology required in a copper damascene manufacturing process. Novellus recognized the increasing importance of the CMP process step, so in 2002 we acquired SpeedFam-IPEC, a global supplier of CMP systems used in the fabrication of advanced copper interconnects.
UVTP (Ultra Violet Thermal Processing)
Ultra Violet Thermal Processing is a post-deposition manufacturing step used to change the mechanical characteristics of deposited films. There are currently two applications for UVTP technology: one used with ultra low-k dielectrics to improve the hardness of porous films, and the other used with high stress nitrides to increase the tensile strength in the deposited film, and increase device performance. In a UVTP reactor a dielectric film is exposed to a combination of light and heat in order to modify the film properties. With high stress nitride films, UVTP promotes bond rearrangement and volume contraction to generate the higher stress levels needed for improved device performance. With porous low-k films, UVTP facilitates removal of porogen and mechanically strengthens the film for further processing.